In the transmission of electromagnetic radiation over antennae, amplification is usually necessary to achieve sufficient power to transmit signals by radiating an electromagnetic field. Similarly to receive signals, low level electromagnetic fields need to be amplified to sufficient power levels for circuitry to discern the received signal. The electromagnetic fields may be radiated at various frequencies but typically are associated with radio or microwave frequency ranges. In any case, it is desirable to provide efficient amplification of signals. Efficient amplification is proportional to the gain provided by an amplifier. Thus, it is desirable to increase both the gain and efficiency in the design of amplifiers used to amplify signals.
Prior art high frequency amplifiers typically use discrete components such as discrete capacitors, discrete inductors and discrete transistors because of they are easy to change out or modify if improperly designed or manufactured and are they are relatively inexpensive. Referring now to FIG. 1A, a discrete transistor 100A is illustrated. Discrete transistor 100A is in a packaged form and includes a single transistor circuit on a semiconductor die 102. The base collector and emitter of the discrete transistor 100A are output respectively on the base pin 104, the collector pin 105, and the emitter pin 106. The base pin 104 is coupled to the base of the discrete transistor 100A through the base bond wire 107 and the base bonding pad 110. The collector pin 105 couples to the collector of the discrete transistor 100A through the collector bonding wire 108 and the collector bonding pad 111. The emitter pin 106 couples to the emitter of the discrete transistor 100A through the emitter bonding wire 109 and the emitter bonding pad 112. Referring now to FIG. 1B, a schematic diagram symbol of the idealized discrete transistor 100B is illustrated. Discrete transistor 100B includes the base pin 104, the collector pin 105 and the emitter pin 106. Referring now to FIG. 1C, a schematic diagram of the discrete transistor 100C including parasitic elements is illustrated. In FIG. 1C, discrete transistor Q is illustrated including the parasitic elements associated with the discrete transistor 100A. Discrete transistor 100A has inherent parasitics due to the metal wire routing from each transistor terminal to the bonding pads which are represented by the base inductance L.sub.b, the collector inductance L.sub.c, and the emitter inductance L.sub.e. Inherent in the manufacturing of a transistor are capacitances between terminals. Between the base and collector is a base-collector capacitance C.sub.bc. Between the base and emitter there is a base-emitter capacitance C.sub.be. Between the collector and emitter is a collector emitter-capacitance C.sub.ce. These transistor parasitics are associated with semiconductor physics and the design and manufacture of the transistor in the semiconductor die 102. Parasitic inductances are also associated with the bonding wires 107-109 connected between the bonding pads and the pins 104-106 and the pins themselves. These parasitic inductances from the bonding wires and pins are represented in FIG. 1C as the base bond wire inductance L.sub.bwb, the collector bond wire inductance L.sub.bwc, and the emitter bond wire inductance L.sub.bwe. In the preferred embodiment, transistor Q of discrete transistor 102 is designed and manufactured for the amplification of radio frequency signals. Alternatively, transistor Q may be designed and manufactured to operate within other ranges of transmission carrier frequencies.
Referring now to FIG. 2A, a block diagram symbol of a single-stage amplifier 200 is illustrated. Amplifier 200 is provided with a power supply input through amplifier ground AG. Signals input on the amplifier input A.sub.IN are amplified by a gain to generate the amplifier output A.sub.out. Referring now to FIG. 2B, a typical schematic diagram of the single-stage amplifier 200 is illustrated. The single stage amplifier 200 is illustrated with the idealized discrete transistor 100 of FIG. 1B. The amplifier input A.sub.IN is coupled into the base of the discrete transistor 100 through the blocking capacitor C.sub.block. Amplifier ground AG is directly coupled preferably to the emitter 106 of the discrete transistor 100. However, amplifier ground AG is not directly coupled into the emitter of transistor Q because of the parasitic inductance associated with the emitter and the package connections including a bond wire and the connecting pin itself. The amplifier output A.sub.out is provided at the collector 105 of the discrete transistor 100.
Often times a single amplifier stage is insufficient to provide a sufficient amount of amplification. In order to provide greater amplification, two or more single amplifier stages may be coupled in series together to form a cascaded amplifier. Referring now to FIG. 3A, a block diagram of a cascaded amplifier 300A is illustrated, having N single amplifier stages. Cascaded amplifier input Cin is input into the cascaded amplifier 300A to generate the cascaded amplifier output Cout. The single amplifier stage, having the discrete transistor 100 illustrated in FIG. 2B is exemplary of each of the instances of amplifiers A.sub.1 through A.sub.n. Typically the cascaded amplifier 300A is implemented in a printed circuit board. Each of the amplifier stages are coupled in series together through the use of metallic printed circuit board traces. Except for the last stage, the output from one stage is coupled to the input of the next respective stage. The printed circuit board typically has a power supply provide the board power BP and board ground BG through their respective metal traces. Each of the discrete amplifiers are typically separately coupled to the board power BP and the board ground BG. The separate power coupling through the metal traces forms parasitic inductive components. Between amplifier power AP and board power BP there is a power trace inductance L.sub.PT1 through L.sub.PTn. Similarly, parasitic inductance is formed through the metal trace between the amplifier ground AG and the board ground BG as represented by the ground trace inductances L.sub.gt1 through L.sub.gtn.Each of the amplifier stages has an input inductance associated with the input wire trace of the printed circuit board. These are represented by the input trace inductances L.sub.IT1 through L.sub.Itn. A trace output inductance L.sub.outT is also associated with the final output from the amplifier stage A.sub.n. Because the ground traces are typically connected to the same board ground BG, AC ground loop currents are formed in the inductances L.sub.GT1 through L.sub.GTn when the amplifier is operating to amplify AC signals. In FIG. 3A, the AC ground loop currents i.sub.1 through i.sub.3 are illustrated. Because of the AC ground loop currents, the actual ground voltage provided to the amplifiers A.sub.1 through A.sub.n, is actually elevated above zero volts when amplification occurs. This causes a degradation in the amplification provided by each of the amplifiers A.sub.1 through A.sub.n when the ground coupled at each respective emitter rises.
Alternatively components of a cascaded amplifier may be implemented within an integrated circuit device. Referring now to FIG. 3B, a packaged integrated circuit 300B for a four stage integrated circuit cascade amplifier 300C is illustrated. The packaged integrated circuit 300B has pins 304, 305-305D, 306-306D which connect using bondwires to the die of the four stage integrated circuit cascaded amplifier 300C. Referring now to FIG. 3C, the integrated circuit 300C includes transistors Q1, Q2, Q3, and Q4 and blocking capactors C.sub.B1, C.sub.B2, C.sub.B3, and C.sub.B4. The other elements illustrated in the schematic of FIG. 3C are parasitic components associated with packaging and manufacturing of the integrated circuit. The packaged integrated circuit 300B does not include the pullup inductance L.sub.PU illustrated in FIG. 2B at each collector of each amplifier stage. The pullup inductance L.sub.PU in the case of the packaged integrated circuit 300B is externally connected. Each bipolar junction transistor has a base to collector capacitance C.sub.BC1 -C.sub.BC4 respectively while other parasitic capacitances associated with the transistor are ignored because they have minimal effect. To each connection of the transistor, there is an inductance associated with the metal wire routing on the integrated circuit. In each emitter leg of each bipolar junction transistor, there is inductance L.sub.E1, L.sub.E2, L.sub.E3, and L.sub.E4 respectively associated with the metal wire routing on the integrated circuit. In each collector leg of each bipolar junction transistor, there is inductance L.sub.C1, L.sub.C2, L.sub.C3, and L.sub.C4 respectively associated with the metal wire routing on the integrated circuit. In each of the base leg of each bipolar junction transistor there is inductance L.sub.B1, L.sub.B2, L.sub.B3, L.sub.B4 respectively from the metal wire routing on the integrated circuit. To connect the integrated circuit to a printed circuit board there are bondwires 307, 306A-306D, and 308-308D and their respective pinouts each having a parasitic bond wire inductance associated with them. For the connection to the base of transistor Q1 there is the bond wire/pin-out inductance L.sub.BWB1. For the connection to the collectors of each transistor there are the bond wire/pin-out inductances L.sub.BCW1, L.sub.BWC2, L.sub.BWC3, and L.sub.BWC4 respectively. For the connection to the emitters of each transistor there are the bond wire/pin-out inductances L.sub.BWE1, L.sub.BWE2, L.sub.BWE3, and L.sub.BWE4 respectively. The integration of the cascasded amplifier into integrated circuit 300B provides little reduction of parasitic inductances. Only the bondwire/pinout inductance between collector to base connections of the discrete device cascaded amplifier has been eliminated. The four emitters of the four stage integrated circuit cascade amplifier 300B retain their parasitic inductances (L.sub.E1 and L.sub.BWE1, L.sub.E2 and L.sub.BWE2, L.sub.E3 and L.sub.BWE3, L.sub.E4 and L.sub.BWE4) through each separate connection to board ground through pin VSS1306A, pin VSS2306B, pin VSS3306C, and pin VSS4306D respectively. Additionally, the four collectors of the four stage integrated circuit cascade amplifier 300B retain their parascitic inductances through their respective separate connections C1305A, C2305B, C3305C, and Cout 305D respectively. Otherwise, the integrated circuit 300B is similar to the discrete cascade amplifer 300A.
Referring now to FIG. 4, a more detailed schematic diagram of the first three amplifier stages of the cascaded amplifier of FIG. 3A is illustrated. In FIG. 4, each of the amplifiers A.sub.1 through A.sub.3 have been replaced with their schematic transistor representation of FIG. 2B. Transistor Q1, blocking capacitor C.sub.B1, base-collector capacitance C.sub.BC1, emitter inductance L.sub.E1, and emitter bond wire inductance L.sub.BWE1 are associated with amplifier A1. Transistor Q2, blocking capacitor C.sub.B2, base-collector capacitance C.sub.BC2, emitter inductance L.sub.E2, and emitter bond wire inductance L.sub.BWE2 are associated with amplifier A2. Transistor Q3, blocking capacitor C.sub.B3, base-collector capacitance C.sub.BC3, emitter inductance L.sub.E3, and emitter bond wire inductance L.sub.BWE3 are associated with amplifier A3. FIG. 4 illustrates the more relevant parasitic values associated with the cascaded amplifier while those of insignificance are lumped together to the relevant parasitic values so as not to obscure details of the present invention. The bias resistor RBIAS for each amplifier is also not shown in FIG. 4. The base inductance L.sub.B is insignificant when compared with the base bond wire inductance L.sub.BWB and the input trace inductance L.sub.IT. Additionally, the base current into the base is of a sufficiently low enough value such that all the inductance can be lumped together into L.sub.IT, where L.sub.IT '=L.sub.IT +L.sub.BWB+L.sub.B. In FIG. 4, inductance L.sub.IT1 ' through L.sub.IT3 ' is coupled to the respective base of each transistor amplifier stage. The collector inductance L.sub.c and the collector bond wire inductance L.sub.BWC is insignificant when compared with the pull up inductor L.sub.PU. Thus, the collector inductance can be lumped together as LPU' where L.sub.PU '=L.sub.PU +L.sub.BWC+L.sub.C. FIG. 4 shows the first three amplifier stages with L.sub.PU1 ' through L.sub.UP3 '. The inductance between the emitter and board ground BG in the emitter leg, is the emitter inductance L.sub.E, the emitter bond wire inductance L.sub.BWE and the ground trace inductance L.sub.GT. This inductance is often times referred to as a degeneration inductance. In FIG. 4 ground loop current i.sub.1 flows out of the emitter of transistor Q2 towards ground through inductance L.sub.E2, inductance L.sub.BWE2, inductance L.sub.G2T, back towards transistor Q1 through inductance L.sub.GT1, inductance L.sub.BWE1, inductance L.sub.E1 into the emitter and out the collector of transistor Q1, and forwards towards transistor Q2 through inductance L.sub.IT2 ', capacitance C.sub.B2 and into the base and out the emitter of transistor Q2. Ground current loop i.sub.2 circulates similarly through the components and transistors of the ground current loop between transistors Q2 and Q3. Both ground loop currents i.sub.1 and i.sub.2 flow through the sum of the inductances of L.sub.E2, L.sub.BWE2, and L.sub.GT2 in the emitter leg of transistor Q2. This common inductance between the current loops i.sub.1 and i.sub.2 is referred to as the common ground inductance L.sub.common. A ground return inductance, L.sub.return, is the inductance seen in the ground path by the input ground current loop i.sub.1. The ground return inductance with respect to current i.sub.1 is the sum of the inductance in the prior emitter leg (L.sub.E1, L.sub.BWE1, L.sub.GT1 of amplifier A.sub.1). The common ground inductance L.sub.common and the ground return inductance L.sub.return are parasitic inductances associated with the cascaded amplifier. Because both ground loop currents i.sub.1 and i.sub.2 flow through the common ground inductance L.sub.common found in the emitter leg of transistor Q2, an elevated voltage above ground may be provided to the emitter of the transistor. This can result in reduced base-emitter control voltage V.sub.be such that less amplification is provided by the transistor. From these two ground loop currents, the amplifier power A.sub.p provided by a single stage discrete transistor amplifier can be approximated by the equation for A.sub.p. ##EQU1##
In the case of analyzing A.sub.P for amplifier stage 2, EQU L.sub.common =L.sub.E2 +L.sub.BWE2 +L.sub.GT2 and L.sub.return.apprxeq.L.sub.E1 +L.sub.BWE1 +L.sub.GT1 (EQ. 2).
In the equation for amplifier power A.sub.p, .omega. is the frequency in radians where .omega.=2.pi.f, B.sub.ac is the AC Beta of the transistor and B.sub.ac =i.sub.out /i.sub.in, L.sub.common is the sum of inductances in the emitter leg (in the case of amplifier A.sub.2 this is L.sub.E2, L.sub.BWE2, and L.sub.GT2) while the L.sub.return is approximated by the sum of the inductance in the prior emitter leg (L.sub.E1, L.sub.BWE1, L.sub.GT1 of amplifier A.sub.1). Thus, the inductance between the emitter and board ground BG in the emitter leg of the transistor has a significant impact on the gain of a single amplifier stage.
The parasitic inductance in each emitter leg decreases the gain of each respective amplifier stage. The decrease in gain of each amplifier stage decreases the overall efficiency of the power amplifier. The total power efficiency .theta..sub.Total of a five stage cascaded amplifier may be approximated by using EQ. 3. ##EQU2##
In EQ. 3, .theta..sub.n is the efficiency of each respective numbered amplifier stage where n varies from 1 through 5. From this equation it can be seen that if inductance in the emitter legs of the amplifier stages reduces the gain of the respective stage, the efficiency of the cascaded amplifier will be reduced. Efficiency of amplifiers is particularly important in battery operated systems, such as cellular telephones, to increase the lifetime of the battery or the period between charging a rechargeable battery. Therefore, it is desirable to reduce or eliminate the inductance in the emitter leg of the transistor in each amplifier stage in order to improve the gain and power efficiency of a cascaded series of amplifiers,